1. Field of the Invention
The present invention relates generally to a power-up reset circuit, and more particularly, to a power-up reset circuit for reducing power consumption.
2. Description of the Related Art
A power-up operation may include a power voltage applied to a semiconductor memory device. While the semiconductor memory device undergoes the power-up operation, the power voltage may not be completely stable. The instability of the power voltage may make it difficult to interpret voltage levels (e.g., high and/or low voltage levels) within the semiconductor memory device. When the power voltage is first applied during power-up, the semiconductor memory device may require initialization. Thus, conventional semiconductor memory devices may include a power-up reset circuit which may prevent the semiconductor memory device from operating and may initialize the semiconductor memory device during the power-up operation.
FIG. 1 illustrates a block diagram of a conventional power-up reset circuit 100. Referring to FIG. 1, the power-up reset circuit 100 may include a power voltage detecting portion 10 and a signal generating portion 20. The power voltage detecting portion 10 may include a detecting portion 12 and an output portion 14. The detecting portion 12 may include resistors R1 and R2. The output portion 14 may include a resistor R3 and an NMOS transistor N1. The signal generating portion 20 may include inverters IV1, IV2 and IV3.
The power voltage detecting portion 10 may detect a voltage level (e.g., a high voltage level, a low voltage level, etc.) of a power voltage Vcc applied from an external portion (not shown) to output a voltage detecting signal VD. The detecting portion 12 may output a node voltage VA in response to the power voltage Vcc. During a power-up operation, the power voltage Vcc may gradually increase. The node voltage VA at a node A of the detecting portion 12 may increase with the power voltage Vcc. The voltage levels of the node voltage VA and the power voltage VA may be based on the power voltage Vcc and the resistances of resistors R1 and R2. The detecting portion 12 may output the node voltage VA.
The output portion 14 may output the power detecting signal VD in response to the node voltage VA received from the detecting portion 12. If the node voltage VA is lower than a threshold voltage level, the NMOS transistor N1 may be turned off. The voltage detecting signal VD may be set to a first voltage level (e.g., a high voltage level) in response to the NMOS transistor N1 turning off. Alternatively, if the node voltage VA is higher than the threshold voltage level, the NMOS transistor N1 may be turned on. The voltage detecting signal VD may be set to a second voltage level (e.g., a low voltage level) in response to the NMOS transistor N1 turning on.
The signal generating portion 20 may invert the voltage detecting signal VD. The inverted signal may be delayed by a given amount of time (e.g., due to the inverting operation). The inverted signal may be output as a reset signal VCCH at a given voltage level (e.g., a high voltage level or the power voltage Vcc level, a low voltage level or ground, etc.).
The power-up reset circuit 100 may output the reset signal VCCH at the second voltage level (e.g., the low voltage level) if the power voltage Vcc is lower than a threshold voltage level. Alternatively, the power-up reset circuit 100 may output the reset signal VCCH at the first voltage level (e.g., a high voltage level or the power voltage Vcc) if the power voltage Vcc is higher than the threshold voltage level.
The power-up reset circuit 100 may have increased power consumption due to a standby current flowing through the power voltage detecting portion 10 during a normal operation. In other words, since the standby current may flow through the detecting portion 12 and the NMOS transistor N1 may be turned on during a normal operation, the standby current may flow through the output portion 14.
Further, when a power dip (i.e., a temporarily reduced power voltage Vcc) occurs during a normal operation, an abnormal (e.g., unstable) operation of the conventional semiconductor memory device may occur (e.g., since the reset signal VCCH may transition to the second voltage level).
FIG. 2 is a graph illustrating the reset signal VCCH and the power voltage Vcc of the power-up reset circuit 100 of FIG. 1 during operation. In FIG. 2, a dotted line may denote the power voltage Vcc and a solid line combined with the dotted line may denote the reset signal VCCH.
Referring to FIG. 2, during the power-up operation, the power voltage Vcc increases (e.g., before t1). The power voltage Vcc may reach a threshold voltage level V1 at t1. When the power voltage Vcc reaches the threshold voltage level V1 at t1, a reset signal VCCH may transition from the second voltage level (e.g., a low voltage level) to the first voltage level (e.g., a high voltage level or the power voltage level Vcc). When the reset signal VCCH transitions to the first voltage level, a conventional semiconductor memory device including the power-up reset circuit 100 may begin normal operation.
However, if a power dip occurs during the normal operation, the conventional semiconductor memory device may discontinue normal operation (e.g., because the conventional semiconductor memory device believes that the power voltage Vcc has been shut off). Referring to FIG. 2, a power dip is illustrated between t2 and t3. Thus, the power voltage Vcc drops below the threshold voltage level V1 (at t2) and the reset signal VCCH transitions from the first voltage level to the second voltage level. The power voltage Vcc may rise above the threshold voltage level V1 (at t3). As shown, the reset signal VCCH may transition from the second voltage level back to the first voltage level (at t3). Thus, a power dip may interrupt normal operation in conventional semiconductor memory devices.
FIG. 3 illustrates a block diagram of another conventional power-up reset circuit 300. As described above with respect to the power-up reset circuit 100 of FIG. 1, the power-up reset circuit 300 of FIG. 3 may include the power voltage detecting portion 10. The power-up reset circuit 300 may further include a signal generating portion 22, a switch portion 30, a cut off portion 40, and a latch portion 50.
The power voltage detecting portion 10 of FIG. 3 is described above with respect to FIG. 1 and will not be described further. The signal generating portion 22 may include inverters IV1 and IV2. The switch portion 30 may include a PMOS transistor P1. The cut off portion 40 may include an inverter IV4, PMOS transistors P2 and P3, and NMOS transistors N2 and N3. The latch portion 50 may include an inverter IV5 and an NMOS transistor N4.
The PMOS transistor P1 may include a gate where the reset signal VCCH may be received (e.g., the reset signal VCCH output from the power-up reset circuit 300 may be fed back to the PMOS transistor P1). The PMOS transistor P1 may be set (e.g., turned on or off) in response to the reset signal VCCH to control operation of the power voltage detecting portion 10. If the reset signal VCCH is at the second voltage level, the PMOS transistor P1 may be turned on, and the power voltage detecting portion 10 may begin operation.
If the power voltage Vcc increases above the threshold voltage level, the reset signal VCCH may transition to the first voltage level, the PMOS transistor P1 may be turned off, and the NMOS transistor N1 of the power voltage detecting portion 10 may be turned off. As a result, the power voltage detecting portion 10 may not operate, and a standby current which may flow through the detecting portion 12 and the output portion 14 may be reduced.
The cut off portion 40 may be isolate from the latch portion 50 and/or the signal generating portion 22 may be isolated from the power voltage detecting portion 10 in response to the reset signal VCCH. If the reset signal VCCH is at the second voltage level, the PMOS transistors P3 and the NMOS transistor N3 may be turned on, and a voltage detecting signal VD may be output from the power voltage detecting portion 10. The voltage detecting signal VD may be received by the latch portion 50. Alternatively, if the reset signal VCCH is at the first voltage level, the PMOS transistors P3 and the NMOS transistor N3 may be turned off, and the power voltage detecting portion 10 may be isolated from the latch portion 50.
An example where the latch portion 50 may prevent the reset signal VCCH from transitioning to the second voltage level during normal operation will now be described. Referring to FIG. 3, if the voltage detecting signal VD received from the cut off portion 40 is at the first voltage level, the inverter IV5 may output a latch signal VL at the second voltage level. If the power voltage Vcc increases (e.g., above the threshold voltage level), the voltage detecting signal VD may transition to the first voltage level, the inverter IV5 may output the latch signal VL at the first voltage level and the NMOS transistor N4 may be turned on. In response to the NMOS transistor N4 turning on, an input end of the inverter IV5 may be set to the second voltage level, thereby preventing an output of the inverter IV5 from transitioning to the second voltage level. Thus, the reset signal VCCH may not transition to the second voltage level in the above-described example.
The signal generating portion 22 may delay the latch signal VL. The delayed signal may be output as the reset signal VCCH at a given voltage level (e.g., a high voltage level or the power voltage Vcc level, a low voltage level or ground, etc.).
Referring to FIG. 3, the operation of the power-up reset circuit 300 may not be interrupted if the power voltage Vcc drops below the threshold voltage level. If the power voltage Vcc increases above the threshold voltage level, the reset signal VCCH may be set to the power voltage Vcc level. The switch portion 30 may be turned off to stop an operation of the power voltage detecting portion 10, thereby reducing the standby current. Further, the cut off portion 40 may isolate the power voltage detecting portion 10 from the latch portion 50 and the signal generating portion 22. The latch portion 50 may prevent the reset signal VCCH from transitioning to the second voltage level again during a normal operation. Thus, after the reset signal VCCH is set to the first voltage level, the reset signal VCCH may remain at the first voltage level (e.g., the power voltage Vcc).
FIG. 4 is a graph illustrating the reset signal VCCH and the power voltage Vcc of the power-up reset circuit 300 of FIG. 3. In FIG. 4, a dotted line may denote the power voltage Vcc and a solid line combined with the dotted line may denote the reset signal VCCH.
Referring to FIG. 4, the power voltage Vcc may increase above the threshold voltage level V1 (at t1). The reset signal VCCH may transition from the second voltage level to the first voltage level (at t1) (e.g., the power voltage level Vcc). The reset signal VCCH may be fixed to the power voltage Vcc level (at t1) (e.g., by the latch portion 50) such that the reset signal VCCH may not transition to the second voltage level when a power dip occurs (between t2 and t3).
However, incorrect information (e.g., from a previous operation) may be stored in the power-up reset circuit 300 during the power-up operation due to characteristics of the latch portion 50. The latch signal VL may be stored at the first voltage level at the beginning of the power-up operation. This may cause the reset signal VCCH to be output at the first voltage level. Thus, the power-up reset circuit may not operate during the power-up operation, and the reset signal VCCH may not be generated correctly. An additional reset circuit may be required to cause the reset signal VCCH to be output at the second voltage level during a power reset.